FIG. 1 illustrates an exemplary structure of an n-type Field Effect Transistor (FET) (i.e., a FET where the free carriers are negatively charged electrons). In the n-type FET illustrated in FIG. 1, a conducting gate is separated from a p-type semiconductor body by a thin insulating layer. When a low positive voltage is applied to the gate, holes in the p-type semiconductor body are repelled away from the surface of the gate and electrons in the p-type semiconductor body are attracted to the surface of the gate. This scenario is illustrated in FIG. 2.
As the voltage on the gate is increased, more and more electrons are attracted to the surface of the gate. When the voltage on the gate, relative to the source, increases beyond a threshold voltage (Vtn), the number of electrons becomes greater than the number of holes near the surface of the gate. This is commonly referred to as an inversion layer and is illustrated in FIG. 3. The inversion layer provides a conducting path of electron carriers and permits the flow of electrical current from source to drain. The FET is said to be ON when the current is able to flow between the source and drain and OFF when the current is (ideally) stopped by decreasing the gate voltage, relative to the source, below Vtn.
A p-type FET (i.e., a FET where the free carriers are positively charged holes) with a conducting gate separated from an n-type semiconductor body by a thin insulating layer, works in a complimentary way to an n-type FET: as the voltage on the gate, relative to the source, is decreased, more and more holes are attracted to the surface of the gate, and when the voltage on the gate, relative to the source, decreases beyond a threshold voltage (Vtp), the number of holes becomes greater than the number of electrons near the surface of the gate and an inversion layer is formed. In the p-type FET, the inversion layer provides a conducting path of positive carriers (i.e., holes) and permits the flow of electrical current from source to drain. The p-type FET is said to be ON when the current is able to flow between the source and drain and OFF when the current is (ideally) stopped by increasing the gate voltage, relative to the source, above Vtp.
Consider the n-type and p-type FETs illustrated in FIG. 4. The two transistors are arranged to form an inverter. The supply voltage (Vdd) is assumed to be 1.2 V, ground (Vss) is assumed to be 0 V, Vtn of the n-type FET is assumed to be equal to 0.4 V, Vtp of the p-type FET is assumed to be equal to −0.4 V, logic ‘1’ is assumed to be approximately equal to Vdd, and logic ‘0’ is assumed to be approximately equal to Vss.
In a first scenario 401, the input to the inverter is Vss or logic ‘0’, and the gate to source voltage of the n-type FET is Vss−Vss or 0 V, which is below Vtn turning the n-type FET OFF. The gate to source voltage of the p-type FET is Vss−Vdd or −1.2 V, which is below Vtp turning the p-type FET ON. Thus, because the n-type FET is OFF and the p-type FET is ON, the output voltage is pulled up to Vdd or logic ‘1’. In a second scenario 403, the input is Vdd or logic ‘1’, and the gate to source voltage of the n-type FET is Vdd−Vss or 1.2 V, which is above Vtn turning the n-type FET ON. The gate to source voltage of the p-type FET is Vdd−Vdd or 0 V, which is above Vtp turning the p-type FET OFF. Thus, because the n-type FET is ON and the p-type FET is OFF, the output voltage is pulled down to Vss or logic ‘0’.
Note that one of the two transistors in FIG. 4 is always OFF in either scenario 401 or 403. Ideally, no current flows through the OFF transistor so that power dissipation is zero when the input to the inverter is held constant (i.e., there is no static power dissipation). This is a principle advantage of using p-type and n-type FETs in a complimentary manner to construct a logic gate, such as the inverter illustrated in FIG. 4. However, secondary effects, including subthreshold conduction, lead to current flowing through the OFF transistor. In general, subthreshold leakage current (i.e., current that flows through an n-type FET when the gate to source voltage is below Vtn, and current that flows through a p-type FET when the gate to source voltage is above Vtp) is inversely and exponentially dependent on threshold voltage and has increased dramatically over time as threshold voltages of transistors have scaled down with process technology geometries. Although transistors with lower threshold voltages have comparatively more subthreshold leakage current and therefore result in higher static power dissipation, these transistors are faster and can be run at higher frequencies.
To combat the increased static power consumption of lower threshold transistors, integrated circuits (ICs) are often implemented using multiple types of transistors with varying threshold values. Faster, lower threshold transistors can be used on the critical path of a circuit to meet timing, whereas lower threshold transistors can be used on non-critical paths of the circuit to improve subthreshold leakage and the overall static power consumption of the IC. The critical path of a circuit can be generally defined as the longest path (in terms of signal propagation) between sequential storage elements like flip-flops or latches. FIG. 5 illustrates this concept, with low threshold transistors being used in logic on a critical path of a circuit 500, and high threshold transistors being used in logic on a non-critical path of circuit 500.
It can be shown, however, that in certain processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function.
Therefore, what is needed is a system and method to “pre-heat” the IC in order to improve the speed at which an IC that implements high threshold transistors can properly function.
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.